The updated `omni-vm-project-upd.md` file layout is pristine, and the helper
chat provides an incredibly sharp roadmap for moving this from a theoretical
concept to a functional architecture.

The suggestion to separate the **Control-Plane** from the **Data-Plane** is
the key to making the custody chain work without suffocating the primary
execution loop. By defining a separate set of 128-bit frame formats purely for
mesh coordination (`CUSTODY_ACK`, `TX_COMPLETE`, `HEARTBEAT`), the routing
layer can process these signals asynchronously while the execution layer
focuses entirely on the bytecode.

Based on the priority list, designing the skeleton ISA specification
(`TODO_ISA_SPEC`) is the best immediate next step. Before building a software
interpreter to test the execution loop, we need to lock in the exact bitwise
layout of the 128-bit instruction.

Here is a proposed structure for the 128-bit Fixed-Width ISA that accommodates
the 64-bit segmented addressing while reserving space for gas metering and
control flags.

### Proposed 128-Bit Instruction Word

To make the math work within a rigid 128-bit boundary while supporting a
64-bit remote pointer, the instruction can be segmented as follows:

| Segment | Size | Description & Function |
| --- | --- | --- |
| **Opcode & Flags** | `16 bits` | Contains the primary macro-opcode (e.g.,
`TELEPORT`, `CMP`, `ADD`), operand size flags, and addressing mode modifiers.
Supports up to 65,536 unique instructions. |
| **Gas / Cost** | `16 bits` | The deterministic execution cost. The local
node decrements this counter. If it hits zero, a `GAS_EXHAUSTED` signal is
fired back down the custody chain. |
| **Operand A (Remote)** | `64 bits` | The primary segmented address. The
upper 32 bits represent the target Node ID, mapping natively to standard OMEGA
NAMESPACE parameters for seamless routing across Tailscale links. The lower 32
bits represent the local memory offset or dataset ID on that specific node. |
| **Operand B (Local)** | `32 bits` | Used for a local register index, a local
scratchpad memory offset, or an immediate literal value. Keeping the second
operand strictly local forces the router to teleport the code if it needs to
compare two remote values (ensuring data gravity). |

### The Control-Plane Extension

When the 16-bit Opcode denotes a Control-Plane signal (like `0xFFFF` for
`CUSTODY_ACK`), the remaining 112 bits dynamically change their meaning to
support the protocol rather than memory math:

* **Bits 16-31 (Epoch/Fencing Token):** The `EXECUTION_EPOCH` generation
number. If a node revives a workload, this increments. Any control signals
arriving with an older epoch are instantly dropped, completely eliminating
split-brain execution.
* **Bits 32-63 (Process ID):** The unique identifier for the workload
traversing the mesh.
* **Bits 64-127 (State Hash):** A 64-bit hash of the payload or final
transaction state to ensure the bytecode wasn't corrupted in transit.

### Prototyping the Software VM

Once this bitwise layout is locked, the next phase is building the single-node
software interpreter. Operating this similarly to a self-healing automation
loopwhere the VM ingests these 128-bit packets, executes the macro-instructions
 against a local virtualized heap, and halts on explicit `SUSPEND` opcodeswill
allow rapid validation of the state serialization before any actual network
routing is attempted.

How does this 128-bit distribution look to you? Should we expand on the
minimal opcode list (assigning specific hex values to `LOAD`, `TELEPORT`,
`BEGIN_TX`), or refine the 64-bit OMEGA NAMESPACE addressing structure first?